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2.5V LVDS, 1:4 GLITCHLESS CLOCK BUFFER TERABUFFERTM II General Description
The IDT5T93GL04 2.5V differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T93GL04 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source up to 450MHz. Selectable inputs are controlled by SEL. During the switchover, the output will disable low for up to three clock cycles of the previously-selected input clock. The outputs will remain low for up to three clock cycles of the newly-selected clock, after which the outputs will start from the newly-selected input. A FSEL pin has been implemented to control the switchover in cases where a clock source is absent or is driven to DC levels below the minimum specifications. The IDT5T9304 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.
IDT5T93GL04
Features
* * * * * * * * * * * * *
Guaranteed low skew: <50ps (maximum) Very low duty cycle distortion: <100ps (maximum High speed propagation delay: <2.2ns (maximum) Up to 450MHz operation Selectable inputs Hot insertable and over-voltage tolerant inputs 3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML or LVDS input interface Selectable differential inputs to four LVDS outputs Power-down mode At power-up, FSEL should be LOW 2.5V VDD -40C to 85C ambient operating temperature Available in TSSOP package
Applications
*
Clock distribution
Pin Assignment
GND PD FSEL VDD Q1 Q1 Q2 Q2 VDD SEL G GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 A2 A2 GND VDD Q3 Q3 Q4 Q4 VDD GL A1 A1
24-Lead TSSOP 4.4mm x 7.8mm x 1.0mm package body G Package Top View
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Block Diagram
GL G
OUTPUT CONTROL
Q1 Q1
PD
OUTPUT CONTROL
Q2 Q2
A1 A1
1
OUTPUT CONTROL
Q3 Q3
A2 A2
0
OUTPUT CONTROL
Q4 Q4
SEL FSEL
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Table 1. Pin Descriptions
Name A[1:2] Input Type Adjustable
(1, 4)
Description Clock input. A[1:2] is the "true" side of the differential clock input.
A[1:2]
Input
Complementary clock inputs. A[1:2] is the complementary side of A[1:2]. For LVTTL single-ended operation, A[1:2] should be set to the desired toggle Adjustable (1, 4) voltage for A[1:2]: 3.3V LVTTL VREF = 1650mV 2.5V LVTTL VREF = 1250mV LVTTL Gate control for differential outputs Q1 and Q1 through Q4 and Q4. When G is LOW, the differential outputs are active. When G is HIGH, the differential outputs are asynchronously driven to the level designated by GL(2). Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true" outputs disable LOW and "complementary" outputs disable HIGH. Clock outputs. Complementary clock outputs. Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1 and A1. Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both "true" and "complementary" outputs will pull to VDD. Set HIGH for normal operation.(3) At a rising edge, FSEL forces select to the input designated by SEL. Set LOW for normal operation. At power-up, FSEL should be LOW. Power supply for the device core and inputs. Ground.
G
Input
GL Q[1:2] Q{1:2} SEL
Input Output Output Input
LVTTL LVDS LVDS LVTTL
PD
Input
LVTTL
FSEL VDD GND
Input
LVTTL Power Power
NOTES: 1. Inputs are capable of translating the following interface standards: Single-ended 3.3V and 2.5V LVTTL levels Differential HSTL and eHSTL levels Differential LVEPECL (2.5V) and LVPECL (3.3V) levels Differential LVDS levels Differential CML levels 2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after asserting PD. 4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.
Table 2. Pin Characteristics (TA = +25C, F = 1.0MHz)
Symbol CIN Parameter Input Capacitance Test Conditions Minimum Typical Maximum 3 Units pF
NOTE: This parameter is measured at characterization but not tested.
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Function Tables
Table 3A. Gate Control Output Table
Codntrol Output GL 0 0 1 1 G 0 1 0 1 Q[1:4] Toggling LOW Toggling HIGH Outputs Q[1:4] Toggling HIGH Toggling LOW
Table 3B. Input Selection Table
Selection SEL pin 0 1 Inputs A2/A2 A1/A1
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characterisitcs is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.. Item Power Supply Voltage, VDD Input Voltage, VI Output Voltage, VO Not to exceed 3.6V Storage Temperature, TSTG Junction Temperature, TJ Rating -0.5V to +3.6V -0.5V to +3.6V -0.5 to VDD +0.5V -65C to 150C 150C
Recommended Operating Range
Symbol TA VDD Description Ambient Operating Temperature Internal Power Supply Voltage Minimum -40 2.3 Typical +25 2.5 Maximum +85 2.7 Units C V
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DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics(1), TA = -40C to 85C
Symbol IDDQ ITOT IPD Parameter Quiescent VDD Power Supply Current Total Power VDD Supply Current Total Power Down Supply Current Test Conditions VDD = Max., All Input Clocks = LOW(2); Outputs enabled VDD = 2.7V; FREFERENCE Clock = 450MHz PD = LOW Minimum Typical(2) Maximum 240 250 5 Units mA mA mA
NOTE 1: These power consumption characteristics are for all the valid input interfaces and cover the worst case conditions. NOTE 2: The true input is held LOW and the complementary input is held HIGH. Table 4B. LVTTL DC Characteristics(1), TA = -40C to 85C Symbol IIH IIL VIK VIN VIH VIL VTHI VREF Parameter Input High Current Input Low Current Clamp Diode Voltage DC Input Voltage DC Input High Voltage DC Input Low Voltage DC Input Threshold Crossing Voltage Single-Ended Reference Voltage (3) 3.3V LVTTL 2.5V LVTTL VDD/2 1.65 1.25 Test Conditions VDD = 2.7V VDD = 2.7V VDD = 2.3V, IIN = -18mA -0.3 1.7 0.7 -0.7 Minimum Typical(2) Maximum 5 5 -1.2 3.6 Units A A V V V V V V V
NOTE 1: See Recommended Operating Range table. NOTE 2: Typical values are at VDD = 2.5V, +25C ambient. NOTE 3: For A[1:2] single-ended operation, A[1:2] is tied to a DC reference voltage.
Table 4C. Differential DC Characteristics(1), TA = -40C to 85C
Symbol IIH IIL VIK VIN VDIF VCM Parameter Input High Current Input Low Current Clamp Diode Voltage DC Input Voltage DC Differential Voltage(3) Test Conditions VDD = = 2.7V VDD = = 2.7V VDD = 2.3V, IIN = -18mA -0.3 0.1 0.05 VDD -0.7 Minimum Typical(2) Maximum 5 5 -1.2 3.6 Units A A V V V V
DC Common Mode Input Voltage
NOTE 1: See Recommended Operating Range table. NOTE 2: VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. NOTE 3: VCM specifies the maximum allowable range of (VTR + VCP) /2. NOTE 4: Typical values are at VDD = 2.5V, +25C ambient.
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Table 4D. LVDS DC Characteristics(1), TA = -40C to 85C
Symbol VOT(+) VOT(-) VOT VOS VOS IOS IOSD Parameter Differential Output Voltage for the True Binary State Differential Output Voltage for the False Binary State Change in VOT Between Complementary Output States Output Common Mode Voltage (Offset Voltage) Change in VOS Between Complementary Output States Outputs Short Circuit Current Differential Outputs Short Circuit Current VOUT+ and VOUT- = 0V VOUT+ = VOUT- 12 6 1.125 1.2 Test Conditions Minimum 247 247 Typical(2) Maximum 454 454 50 1.375 50 24 12 Units mV mV mV V mV mA mA
NOTE 1: See Recommended Operating Range table. NOTE 2: Typical values are at VDD = 2.5V, +25C ambient.
AC Electrical Characteristics
Table 5A. HSTL Differential Input AC Characteristics, TA = -40C to 85C
Symbol VDIF VX DH VTHI tR / tF Parameter Input Signal Swing(1) Point(2) Level(3) Value 1 750 50 Crossing Point 2 Rate(4) Units V mV % V V/ns
Differential Input Signal Crossing Duty Cycle
Input Timing Measurement Reference Input Signal Edge
NOTE 1.The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. NOTE 2.A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals. NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
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Table 5B. eHSTL AC Differential Input Characteristics, TA = -40C to 85C
Symbol VDIF VX DH VTHI tR / tF Parameter Input Signal Swing
(1) (2)
Value 1 900 50
(3)
Units V mV % V V/ns
Differential Input Signal Crossing Point Duty Cycle
Input Timing Measurement Reference Level Input Signal Edge Rate
(4)
Crossing Point 2
NOTE 1.The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. NOTE 2.A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals. NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
Table 5C. LVPECL (2.5V) and LVPECL (3.3V) Differential Input AC Characteristics, TA = -40C to 85C
Symbol VDIF VX DH VTHI tR / tF Parameter Input Signal Swing(1) LVEPECL LVPECL Maximum 732 1082 1880 50 Level(3) Crossing Point 2 Rate(4) Units mV mV m % V V/ns
Differential Input Cross Point Voltage(2) Duty Cycle Input Timing Measurement Reference Input Signal Edge
NOTE 1.The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. NOTE 2.A 1082mV LVEPECL (2.5V) and 1880mV LVPECL (3.3V) crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals. NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
Table 5D. LVDS Differential Input AC Characteristics, TA = -40C to 85C
Symbol VDIF VX DH VTHI tR / tF Parameter Input Signal Swing(1) Voltage(2) Level(3) Maximum 400 1.2 50 Crossing Point 2 Rate(4) Units mV V % V V/ns
Differential Input Cross Point Duty Cycle
Input Timing Measurement Reference Input Signal Edge
NOTE 1.The 400mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions. NOTE 2.A 1.2V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under actual use conditions. NOTE 3.In all cases, input waveform timing is marked at the differential cross-point of the input signals. NOTE 4.The input signal edge rate of 2V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
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Table 5E. AC Differential Input Characteristics(1), TA = -40C to 85C
Symbol VDIF VX VCM VIN Parameter AC Differential Voltage
(2)
Minimum 0.1 0.05 0.05 -0.3
(3)
Typical
Maximum 3.6 VDD VDD 3.6
Units V V V V
Differential Input Cross Point Voltage Common Mode Input Voltage Range Input Voltage
NOTE 1.The output will not change state until the inputs have crossed and the minimum differential voltage range defined by VDIF has been met or exceeded. NOTE 2.VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The AC differential voltage must be achieved to guarantee switching to a new state.. NOTE 3.IVCM specified the maximum allowable range of (VTR + VCP) /2.
Table 5E. AC Characteristics(1,5), TA = -40C to 85C
Symbol tsk(o) t tsk(p) tsk(pp) tpLH tpHL fo tPGE tPGD tPWRDN tPWRUP tR / tF Parameter Same Device Output Pin-to-Pin Skew Pulse Skew(3) Skew(4) A Crosspoint to Qn/Qn Crosspoint 1.5 1.5
(2)
Test Conditions
Minimum
Typical
Maximum 50 100 300 2.2 2.2 450 3.5
Units ps ps ps ns ns MHz ns
Part-to-Part
Propagation Delay, Low-to-High Propagation Delay, High-to-Low Frequency Range(6)
Output Gate Enable Crossing VTHI-to-Qn/Qn Crosspoint Output Gate Enable Crossing VTHI-to-Qn/Qn Crosspoint Driven to GL Designated Level PD Crossing VTHI-to-Qn = VDD, Qn = VDD Output Gate Disable Crossing VTHI to Qn/Qn Driven to Designated Level Output Rise/Fall Time(6) 20% to 80% 100
3.5 100 100 500
ns S S ps
NOTE 1. AC propagation measurements should not be taken within the first 100 cycles of startup. NOTE 2. Skew measured between crosspoints of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device. NOTE 3. Skew measured is the difference between propagation delay times tpHL and tpLH of any differential output pair under identical input and output interfaces, transitions and load conditions on any one device. NOTE 4. Skew measured is the magnitude of the difference in propagation times between any single differential output pair of two devices, given identical transitions and load conditions at identical VDD levels and temperature. NOTE 5. All parameters are tested with a 50% input duty cycle. NOTE 6. Guaranteed by design but not production tested.
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Differential AC Timing Waveforms
Output Propagation and Skew Waveforms
1/fo
A[1:2] - A[1:2]
+ VDIF VDIF = 0 - VDIF tPLH tPHL + VDIF VDIF = 0 - VDIF tSK(O) + VDIF VDIF = 0 - VDIF
Qn - Qn tSK(O)
Qm - Qm
NOTE 1: Pulse skew is calculated using the following expression: tsk(p) = |tpHL - tpLH| Note that the tpHL and tpLH shown above ae not valid measurements for this calculation because they are not taken from the same pulse. NOTE 2: AC propagation measurements should not be taken within the first 100 cycles of startup.
Differential Gate Disabled/Endable Showing Runt Pulse Generation
+ VDIF VDIF = 0 - VDIF VIH VTHI VIL tPLH G VIH VTHI VIL tPGD tPGE + VDIF VDIF = 0 - VDIF
A[1:2] - A[1:2]
GL
Qn - Qn
NOTE 1: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time the G signal to avoid this problem.
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Glitchless Output Operation with Switching Input Clock Selection
A1 - A1
+ VDIF VDIF = 0 - VDIF + VDIF VDIF = 0 - VDIF VIH VTHI VIL + VDIF VDIF = 0 - VDIF
A2 - A2
SEL
Qn - Qn
1. When SEL changes, the output clock goes LOW on the falling edge of the output clock up to three cycles later. The output then stays LOW for up to three clock cycles of the new input clock. After this, the output starts with the rising edge of the new input clock. 2. AC propagation measurements should not be taken within the first 100 cycles of startup.
FSEL Operation for When Current Clock Dies
1. When the differential on the selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this happens, the SEL pin should be toggled and FSEL asserted in order to force selection of the new input clock. The output clock will start up after a number of cycles of the newly-selected input clock. 2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system. 3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that the unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.
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FSEL Operation for When Opposite Clock Dies
1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this happens, the FSEL pin should be asserted in order to force selection of the new input clock. The output clock will start up after a number of cycles of the newly-selected input clock. 2. The FSEL pin should stay asserted until the problem with the dead clock can be fixed in the system. 3. It is recommended that the FSEL be tied HIGH for systems that use only one input. If this is not possible, the user must guarantee that the unused input have a differential greater than or equal to the minimum DC differential specified in the datasheet.
Selection of Input While Protecting Against When Opposite Clock Dies
A1 - A1 +VDIF VDIF=0 -VDIF +VDIF VDIF=0 -VDIF VIH VTHI VIL VIH VTHI VIL
A2 - A2
FSEL
SEL
Qn - Qn
+VDIF VDIF=0 -VDIF
1. If the user holds FSEL HIGH, the output will not be affected by the deselected input clock. 2. The output will immediately be driven to LOW once FSEL is asserted. This may cause glitching on the output. The output will restart with the input clock selected by the SEL pin. 3. If the user decides to switch input clocks, the user must de-assert FSEL, then assert FSEL after toggling the SEL input pin. The output will be driven LOW and will restart with the input clock selected by the SEL pin.
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Power Down Timing
A1 - A1 +VDIF VDIF=0 -VDIF +VDIF VDIF=0 -VDIF VIH VTHI VIL VIH VTHI VIL +VDIF VDIF=0 -VDIF
A2 - A2
G
PD
Qn - Qn
NOTE 1: It is recommended that outputs be disabled before enterning power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after asserting PD. NOTE 2: The Power Down Timing diagram assumes that GL is HIGH. NOTE 3: It should be noted that during power-down mode, the outputs are both pulled to VDD. In the Power Down Timing diagram this is shown when Qn/Qn goes to VDIF = 0.
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Test Circuits and Conditions
Test Circuit for Differential Input
VIN ~50 Transmission Line VDD/2
A
Pulse Generator
VIN ~50 Transmission Line A
D.U.T.
-VDD/2
Scope
50 50
Table 6A. Differential Input Test Conditions
Symbol VTHI VDD = 2.5V 0.2V Crossing of A and A Unit V
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Test Circuit for DC Outputs and Power Down Tests
VDD
Pulse Generator
A A
Qn RL
D.U.T.
RL Qn
VOS
VOD
Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing
VDD/2
CL Z = 50
SCOPE
Pulse Generator
A A
Qn 50
D.U.T.
50 Qn Z = 50 CL -VDD/2
Table 6B. Differential Input Test Conditions
Symbol CL RL VDD = 2.5V 0.2V 0
(1)
Unit pF pF
8(1,2) 50
NOTE 1: Specifications only apply to "Normal Operations" test condition. The TIA/EIA specification load is for reference only. NOTE 2: The scope inputs are assumed to have a 2pF load to ground. TIA/EIA - 644 specifies 5pF between the output pair. With CL = 8pF, this gives the test circuit appropriate 5pF equivalent load.
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Ordering Information
Table 7. Ordering Information
IDT
XXXXX Device Type
XX Package
X Process
I
-40 C to +85 C (Industrial)
PG PGG
Thin Shrink Small Outline Package TSSOP - Green
5T93GL04
2.5V LVDS 1:4 Glitchless Clock Buffer Terabuffer II
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Revision History Sheet
Rev A Table T5E Page 8 Description of Change AC Characteristics Table - added Rise/Fall Time spec. Date 7/10/07
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